1. Field of the Invention
Example embodiments of the present invention generally relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of removing voids formed in a polysilicon layer during a manufacturing of a semiconductor device.
2. Description of the Related Art
Generally, semiconductor memory devices are classified into a volatile memory device, which includes a dynamic random access memory (DRAM) and a static random access memory (SRAM), and a non-volatile memory device, which includes a read only memory (ROM), an electrically erasable and programmable ROM (EEPROM), and a flash memory. Data stored in a volatile memory device are lost after a period of time, however, the data are capable of rapid input/output function. On the contrary, data in a non-volatile memory device are not lost over a period of time, however, the data input/outputs functions are slower than a volatile memory device.
A flash memory device generally inputs/outputs data using Fowler-Nordheim (F-N) tunneling effect or channel hot electron injection effect.
In a general method of manufacturing a flash memory cell, an isolation layer may be provided on a semiconductor substrate An oxide layer may be formed on the isolation layer. The oxide layer may be patterned until a portion of the semiconductor substrate is exposed to form an oxide layer pattern. In a subsequent step, a floating gate may be formed on the exposed portion. A tunnel oxide layer and a first polysilicon layer may be sequentially formed on the resultant structure. The first polysilicon layer may be planarized until the tunnel oxide layer is exposed to form the floating gate. The tunnel oxide layer and the oxide layer pattern may be then partially etched. A dielectric layer may be formed on the resultant structure. A second polysilicon layer, a tungsten silicide layer and a hard mask layer may be sequentially formed on the dielectric layer. The second polysilicon layer, the tungsten layer and the hard mask layer may be patterned to form a control gate. Impurities may be implanted into portions of the semiconductor substrate exposed through the floating gate to form impurity regions.
According to the above-described method, the floating gate is self-aligned by the oxide layer pattern that partially exposes the semiconductor substrate.
Recently, as semiconductor devices have become more integrated, the aspect ratio of an opening, which is defined by an oxide layer pattern partially exposing a semiconductor substrate, has also increased. When the aspect ratio increases, voids may be generated in a polysilicon layer, which is used to fill the opening, due to geometrical dimensions of the oxide layer pattern.
The voids may be exposed when the polysilicon layer is planarized. The voids may deteriorate breakdown voltage characteristics of a dielectric layer on a floating gate, and/or may decrease a coupling ratio of the flash memory device. The voids may also deteriorate leakage current characteristics of the dielectric layer.